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PRELIMINARY
SmartRectifierTM CONTROL IC
Features

Secondary side high speed SR controller DCM, CrCM and CCM flyback topologies 200V proprietary IC technology Max 500KHz switching frequency Anti-bounce logic and UVLO protection 7A peak turn off drive current Micropower start-up & ultra low quiescent current 10.7/14.5V gate drive clamp
IR1167ASPBF IR1167BSPbF
Data Sheet PD60254A

50ns turn-off propagation delay Vcc range from 11.3V to 20V Direct sensing of MOSFET drain voltage Minimal component count Simple design Lead-free Compatible with 1W Standby, Energy Star, CECP, etc.
Description
IR1167S is a smart secondary side driver IC designed to drive N-Channel power MOSFETs used as synchronous rectifiers in isolated Flyback converters. The IC can control one or more paralleled N-MOSFETs to emulate the behavior of Schottky diode rectifiers. The drain to source voltage is sensed differentially to determine the polarity of the current and turn the power switch on and off in proximity of the zero current transition. Ruggedness and noise immunity are accomplished using an advanced blanking scheme and double-pulse suppression which allow reliable operation in continuous, discontinuous and critical current mode operation and both fixed and variable frequency modes.
Package
8-Lead SOIC
IR1167 Application Diagram
Vin
Rs XFM Cs Ci 1 2 3 RMOT 4
Rdc
U1 VCC OVT MOT EN IR1167S VGATE GND VS VD 8
Cdc
6 5 Rg
Co
Rtn
Q1
*Please note that this data sheet contains advanced information that could change before the product is released to production.
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IR1167AS/BS
PRELIMINARY
Absolute Maximum Ratings
Stress beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. All voltages are absolute voltages referenced to GND. Thermal resistance and power dissipation are measured under board mounted and still air conditions.
Parameters
Supply Voltage Enable Voltage Cont. Drain Sense Voltage Pulse Drain Sense Voltage Source Sense Voltage Gate Voltage Operating Junction Temperature Storage Temperature Thermal Resistance Package Power Dissipation ESD Protection Switching Frequency
Symbol
VCC VEN VD VD VS VGATE TJ TS RJA PD VESD fsw
Min.
-0.3 -0.3 -3 -5 -3 -0.3 -40 -55
Max.
20 20 200 200 20 20 150 150 128 970 2 500
Units
V V V V V V C C C/W mW kV kHz SOIC-8
Remarks
VCC=20V, Gate off
SOIC-8, TAMB=25C Human Body Model*
Recommended Operating Conditions
Recommended operating conditions for reliable operation with margin
Parameters
Supply Voltage Operating Junction Temperature Ambient Temperature Switching Frequency
Symbol
VCC TJ TA fsw
Min.
12 -25 -25 40
Max.
18 125 85 400
Units
V C C kHz
Remarks
* Per EIA/JESD22-A114-B( discharging a 100pF capacitor through a 1.5k series resistor).
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IR1167AS/BS
PRELIMINARY
Electrical Characteristics
Supply Section
The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and junction temperature range TJ from 25 C to 125C. Typical values represent the median values, which are related to 25C. If not otherwise stated, a supply voltage of VCC =15V is assumed for test condition.
Parameters
V CC Turn On Threshold V CC Turn Off Threshold (Under Voltage Lock Out) V CC Turn On/Off Hysteresis
Symbol
V CC ON V CC UVLO V CC HYST
Min.
9.8 8.4 1.4
Typ.
10.5 9 1.55 8.5 50 10.3 66 1.8 100 150 2.75 1.6 1.5
Max.
11.3 9.7 1.7 10 65 12 80 2.2 200 200
Units
V V V IR1167A mA IR1167B mA A A V V M GBD V CC =V CC
ON
Remarks
C LOAD =1nF, fsw = 400kHz C LOAD =10nF, f SW = 400kHz C LOAD =1nF, fsw = 400kHz C LOAD =10nF, f SW = 400kHz - 0.1V
Operating Current
ICC
Quiescent Current Start-up Current Sleep Current Enable Voltage High Enable Voltage Low Enable Pull-up Resistance
I QCC I CC START I SLEEP V ENHI V ENLO R EN
V EN =0V, V CC =15V
Comparator Section
Parameters
Turn-off Threshold Turn-on Threshold Hysteresis Input Bias Current Input Bias Current Comparator Input Offset Input CM Voltage Range
Symbol
V TH1 V TH2 V HYST I IBIAS1 I IBIAS2 V OFFSET V CM
Min.
-7 -15 -23 -150
Typ.
-3.5 -10.5 -19 55 1 30
Max.
0 -7 -15 -50 7.5 100 2 2
Units
mV mV mV A A mV V V D = -50mV V D = 200V GBD
Remarks
OVT = 0V, V S =0V OVT floating, V S =0V OVT = V CC, V S =0V
-0.15
One-Shot Section
Parameters
Blanking pulse duration Reset Threshold Hysteresis
Symbol
t BLANK V TH3 V HYST3
Min.
10
Typ.
15 2.5 5.4 40
Max.
20
Units
s V V mV
Remarks
V CC =10V - GBD V CC =20V - GBD V CC =10V - GBD
Minimum On Time Section
Parameters
Minimum on time
Symbol
T ONmin
Min.
190 2.4
Typ.
240 3
Max.
290 3.6
Units
ns s
Remarks
R MOT =5k, V CC =12V R MOT =75k, V CC =12V
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IR1167AS/BS
PRELIMINARY
Gate Driver Section
Parameters
Gate Low Voltage Gate High Voltage Gate High Voltage Rise Time Fall Time Turn on Propagation Delay Turn off Propagation Delay Pull up Resistance Pull down Resistance Output Peak Current (source) Output Peak Current (sink)
**
Symbol
VGLO VGTH VGTH tr1 tr2 tf1 tf2 tDon tDoff rup rdown IO source IO sink
Min.
9.5 12.5
Typ.
0.3 10.7 14.5 30 180 10 30 60 40 4 0.7 2 7
Max.
0.5 12.5 16.5
Units
V V V ns ns ns ns IGATE = 200mA
Remarks
IR1167A - VCC=12V-18V (internally clamped) IR1167B - VCC=12V-18V (internally clamped) CLOAD = 1nF, VCC=12V CLOAD = 10nF, VCC=12V CLOAD = 1nF, VCC=12V CLOAD = 10nF, VCC=12V VDS to VGATE -100mV overdrive VDS to VGATE -100mV overdrive IGATE = 1A - GBD IGATE = -200mA CLOAD = 10nF - GBD CLOAD = 10nF - GBD
80 60
ns ns A A
Guaranteed by Design
STATE AND TRANSITIONS DIAGRAM
POWER ON
Gate Inactive
UVLO MODE
VCC < VCCon Gate Inactive ICC max = 200uA
VCC > VCCon and ENABLE HIGH
VCC < VCCuvlo or ENABLE LOW
NORMAL
Gate Active
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IR1167AS/BS
PRELIMINARY
Block Diagram
MOT VCC VDD
ENA
UVLO & REGULATOR
VDD
VD
Min ON Time VTH1
RESET
VS
DRIVER
VGATE
COM OVT Min OFF Time
Vgate RESET
VTH3
VTH2
VTH1
VTH3
VDS
Lead Assignments & Definitions
Lead Assignment Pin# 1 1 2 3 4 VCC OVT MOT EN VGATE 8 7 6 5 2 3 Symbol VCC OVT MOT EN VD VS GND GATE Description Supply Voltage Offset Voltage Trimming Minimum On Time Enable FET Drain Sensing FET Source Sensing Ground Gate Drive Output
IR1167S
GND VS VD
4 5 6 7 8
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IR1167AS/BS
PRELIMINARY
Detailed Pin Description
GND: Ground
This is ground potential pin of the integrated control circuit. The internal devices and gate driver are referenced to this point. The MOT programming pin controls the amount of minimum on time. Once VTH2 is crossed for the first time, the gate signal will become active and turn on the power FET. Spurious ringings and oscillations can trigger the input comparator off. The MOT blanks the input comparator keeping the FET on for a minimum time. The MOT is programmed between 200ns and 3us (typ.) by using a resistor referenced to GND. The OVT pin will program the amount of input offset voltage for the turn-off threshold VTH1. The pin can be optionally tied to ground, to VCC or left floating, to select 3 ranges of input offset trimming. This programming feature allows for accomodating different RDSon MOSFETs. kelvin contact as close as possible to the power MOSFET source pin.
VD: Drain Voltage Sense
MOT: Minimum On Time
VD is the voltage sense pin for the power MOSFET Drain. This is a high voltage pin and particular care must be taken in properly routing the connection to the power MOSFET drain. Additional filtering and or current limiting on this pin is not recommended as it would limit switching performance of the IC.
VCC: Power Supply
OVT: Offset Voltage Trimming
This is the supply voltage pin of the IC and it is monitored by the under voltage lockout circuit. It is possible to turn off the IC by pulling this pin below the minimum turn off threshold voltage, without damage to the IC. To prevent noise problems, a bypass ceramic capacitor connected to Vcc and GND should be placed as close as possible to the IR1167S. This pin is internally clamped.
GATE: Gate Drive Output
EN: Enable
This is the gate drive output of the IC. Drive voltage is internally limited and provides 2A peak source and 5A peak sink capability. Although this pin can be directly connected to the power MOSFET gate, the use of minimal gate resistor is recommended, expecially when putting multiple FETs in parallel. Care must be taken in order to keep the gate loop as short and as small as possible in order to achieve optimal switching performance.
This pin is used to activate the IC sleep mode by pulling the voltage level below 2.5V (typ). In sleep mode the IC will consume a minimum amount of current. However all switching functions will be disabled and the gate will be inactive.
VS: Source Voltage Sense
VS is the differential sense pin for the power MOSFET Source. This pin must not be connected directly to the power ground pin (7) but must be used to create a
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IR1167AS/BS
PRELIMINARY
STATES OF OPERATION
The IC remains in the UVLO condition until the voltage on the VCC pin exceeds the VCC turn on threshold voltage, VCC ON. During the time the IC remains in the UVLO state, the gate drive circuit is inactive and the IC draws a quiescent current of ICC START. The UVLO mode is accessible from any other state of operation whenever the IC supply voltage condition of VCC < VCC UVLO occurs. The sleep mode is initiated by pulling the EN pin below 2.5V (typ). In this mode the IC is essentially shut down and draws a very low quiescent supply current.
GENERAL DESCRIPTION
The IR1167 Smart Rectifier IC can emulate the operation of diode rectifier by properly driving a Synchronous Rectifier (SR) MOSFET. The direction of the rectified current is sensed by the input comparator using the power MOSFET RDSon as a shunt resistance and the GATE pin of the MOSFET is driven accordingly. Internal blanking logic is used to prevent spurious transitions and guarantee operation in continuous (CCM), discountinuous (DCM) and critical (CrCM) conduction mode.
VGate
UVLO/Sleep Mode
Normal Mode
The IC enters in normal operating mode once the UVLO voltage has been exceeded. At this point the gate driver is operating and the IC will draw a maximum of ICC from the supply voltage source.
VDS VTH2 VTH1 VTH3
Input comparator thresholds
The modes of operation for a Flyback circuit differ mainly for the turn-off phase of the SR switch, while the turn-on phase of the secondary switch (which correspond to the turn off of the primary side switch) is identical. When the conduction phase of the SR FET is initiated, current will start flowing through its body diode, generating a negative VDS voltage across it. The body diode has generally a much higher voltage drop than the one caused by the MOSFET on resistance and therefore will trigger the turn-on threshold VTH2. At that point the IR1167 will drive the gate of MOSFET on which will in turn cause the conduction voltage VDS to drop down. This drop is usually accompained by some amount of ringing, that can trigger the input comparator to turn off; hence, a Minimum On Time (MOT) blanking period is used that will maintain the power MOSFET on for a minimum amount of time. The programmed MOT will limit also the minimum duty www.irf.com 7
Turn-on phase
IR1167AS/BS
PRELIMINARY
cycle of the SR MOSFET and, as a consequence, the max duty cycle of the primary side switch.
DCM/CrCM Turn-off phase
Once the SR MOSFET has been turned on, it will remain on until the rectified current will decay to the level where VDS will cross the turn-off threshold VTH1. This will happen differently depending on the mode of operation. In DCM the current will cross the threshold with a relatively low dI/dt. Once the threshold is crossed, the current will start flowing again through the body diode,
IPRIM
is blanked for a certain amount of time (TBLANK) after VTH1 has been triggered. The blanking time is internally set. As soon as VDS crosses the positive threshold VTH3 also the blanking time is terminated and the IC is ready for next conduction cycle.
CCM Turn-off phase
In CCM mode the turn off transition is much steeper and dI/dt involved is much higher. The turn on phase is identical to DCM or CrCM and therefore wont be repeated here. During the SR FET conduction phase the current will decay linearly, and so will VDS on the SR FET.
IPRIM
VPRIM
T1 ISEC VSEC
T2
T3
time
VPRIM
T1 ISEC
T2
time
time
VSEC
Primary and secondary currents and voltages for DCM mode
IPRIM
Primary and secondary currents and voltages for CCM mode
time
VPRIM
T1 ISEC VSEC
T2
time
Once the primary switch will start to turn back on, the SR FET current will rapidly decrease crossing VTH1 and turning the gate off. The turn off speed is critical to avoid cross conduction on the primary side and reduce switching losses. also in this case a blanking period will be applied, but given the very fast nature of this transition, it will be reset as soon as VDS crosses VTH3.
time
Primary and secondary currents and voltages for CrCM mode
causing the VDS voltage to jump negative. Depending on the amount of residual current, VDS may trigger once again the turn on threshold: for this reason VTH2 www.irf.com 8
IR1167AS/BS
PRELIMINARY
VTH3 ISEC VDS
T1 VTH1
T2 time
VTH2 Gate Drive time Blanking MOT time
Secondary side CCM operation
VTH3 ISEC VDS
T1 VTH1
T2 time
VTH2 Gate Drive time Blanking MOT 10us blanking
Secondary side DCM/CrCM operation
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IR1167AS/BS
PRELIMINARY
10
11
VCC UVLO Threshold (V)
1
10
ISupply (mA)
0.1
9
VCC ON VCC UVLO
0.01 5 10 15 20
8 -50 0 50 100 150
Supply Voltage (V)
Temperature ( C )
Fig 1. Supply Current vs. Supply Voltage
Fig 2. Under Voltage Lockout vs. Temp.
0
0
-5
VTH1 Threshold (mV)
-10
VTH2 Threshold (mV)
-50
-15
-20
-100
-25
OVT = GND OVT = Floating OVT = V CC
-150 -50 0 50 100 150 -50 0 50 100 150
-30
Temperature ( C )
Temperature ( C )
Fig 3. VTH1 vs. Temp.
Fig 4. VTH2 vs. Temp.
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IR1167AS/BS
PRELIMINARY
100
0
Comparator Hysteresis VHYST (mV)
VTH1 Threshold (mV)
-3
50
-6
VS = -150mV VS= 0V VS= +2V
0 -50 0 50 100 150
-9 -50 0 50 100 150
Temperature ( C )
Temperature ( C )
Fig 5. Comparator Hysteresis vs. Temp.
Fig 6. VTH1 vs. Temp. and Common Mode (OVT=GND)
-50
-50
Comparator Hysteresis (mV)
VTH2 Threshold (mV)
-100
-100
VS = -150mV VS= 0V VS= +2V
-150 -50 0 50 100 150
VS = -150mV VS= 0V VS= +2V
-150 -50 0 50 100 150
Temperature ( C )
Temperature ( C )
Fig 7. VTH2 vs. Temp. and Common Mode (OVT=GND)
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Fig 8. Comparator Hysteresis vs. Temp. and Common Mode (OVT=GND)
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IR1167AS/BS
PRELIMINARY
4 100
Input Bias Current (IBIAS2) (A)
Minimum On Time (s)
3
80
60
2
40
1
RMOT = 5k RMOT= 75k
0 -50 0 50 100 150
20
TJ= -25C TJ= 25C TJ= 125C
0 50 100 150 200
0
Temperature ( C )
Drain Sense Voltage (VD) (V)
Fig 9. MOT vs. Temp.
Fig 10. Input Bias Current vs. VD.
20
Maximum Allowable VCC Voltage (V)
18 17 16 15 14 13 12 11 50
Maximum Allowable VCC Voltage (V)
19
Csync = 2nF Csync = 5nF Csync = 8nF Csync = 15nF Csync = 20nF
20 19 18 17 16 15 14 13 12 11
Csync = 2nF Csync = 5nF Csync = 8nF Csync = 15nF Csync = 20nF
100 150 200 250 300 350 400 450 500
50
100 150 200 250 300 350 400 450 500
Max. Synchronous HEXFET Switching Frequency (kHz)
Max. Synchronous HEXFET Switching Frequency (kHz)
Fig 11. Max. VCC Voltage vs. Synchronous Rectifier Switching Freq, TJ=125C, TIC = 85C, external RG=1W, 1 HEXFET Gate Resistance included
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Fig 12. Max. VCC Voltage vs. Synchronous Rectifier Switching Freq, TJ=125C, TIC = 85C, external RG=2W, 1 HEXFET Gate Resistance included
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IR1167AS/BS
PRELIMINARY
20
Maximum Allowable VCC Voltage (V)
Maximum Allowable VCC Voltage (V)
19 18 17 16 15 14 13 12 11 50
Csync = 2nF Csync = 5nF Csync = 8nF Csync = 15nF Csync = 20nF
20 19 18 17 16 15 14 13 12 11
Csync = 2nF Csync = 5nF Csync = 8nF Csync = 15nF Csync = 20nF
100 150 200 250 300 350 400 450 500
50
100 150 200 250 300 350 400 450 500
Max. Synchronous HEXFET Switching Frequency (kHz)
Maximum Synchronous HEXFET Switching Frequency (kHz)
Fig 13. Max. VCC Voltage vs. Synchronous Rectifier Switching Freq, TJ=125C, TIC = 85C, external RG=4W, 1 HEXFET Gate Resistance included
Fig 14. Max VCC Voltage vs. Synchronous Rectifier Switching Freq, TJ=125C, TIC = 85C, external RG=6W, 1 HEXFET Gate Resistance included
Figures 11-14 shows the maximum allowable VCC voltage vs. maximum switching frequency for different loads which are calculated using the design methodology discussed in AN1087.
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IR1167AS/BS
PRELIMINARY
VCC
VCC ON
VCC UVLO
t
UVLO NORMAL UVLO
Fig. 14 - Vcc Under Voltage Lockout
VTH1 V DS V TH2 t Don V Gate 90% 50% 10% t rise
Fig. 15 - Timing Diagrams
t Doff
tfall
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IR1167AS/BS
PRELIMINARY
Case outline
D A 5 B
FOOT PRINT 8X 0.72 [.028]
DIM A b c D
INCHES MIN .0532 .013 .0075 .189 .1497 MAX .0688 .0098 .020 .0098 .1968 .1574
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00
A1 .0040
6 E
8
7
6
5 H 0.25 [.010] A
E
6.46 [.255]
1
2
3
4
e e1 H K L y
.050 BAS IC .025 BAS IC .2284 .0099 .016 0 .2440 .0196 .050 8
1.27 BASIC 0.635 BAS IC 5.80 0.25 0.40 0 6.20 0.50 1.27 8
6X
e
e1
3X 1.27 [.050]
8X 1.78 [.070]
A
K x 45
C 0.10 [.004]
y 8X c
8X b 0.25 [.010]
NOT ES :
A1 CAB
8X L 7
1. DIMENS IONING & TOLERANCING PER AS ME Y14.5M-1994. 2. CONT ROLLING DIMENS ION: MILLIMETER 3. DIMENS IONS ARE S HOWN IN MILLIMETERS [INCHES ]. 4. OUTLINE CONFORMS T O JEDEC OUT LINE MS-012AA.
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUS IONS NOT TO EXCEED 0.15 [.006]. 6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUS IONS NOT TO EXCEED 0.25 [.010]. 7 DIMENSION IS T HE LENGT H OF LEAD FOR SOLDERING TO A S UBSTRATE.
8-Lead SOIC
01-6027 01-0021 11 (MS-012AA)
1167ASPbF
Data and specifications subject to change without notice. Qualification Standards can be found on IRs Web site.
WORLD HEADQUARTERS: 233 Kansas Street, El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 4/2006
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